Development of video codec processor LSIs

Photograph of the world’s first video codec processor in which flexible multi-stage pipeline architecture is implemented.

Fig.1 Photograph of the world’s first video codec processor in which flexible multi-stage pipeline architecture is implemented.

Parallel Block-level pipeline architecture

Fig.2 Parallel Block-level pipeline architecture

Photograph of a 300-MHz, 16-b. 0.5-μm BiCMOS Video Signal Parallel-Pipeline Processor (VSP3)

Fig.3 Photograph of a 300-MHz, 16-b. 0.5-μm BiCMOS Video Signal Parallel-Pipeline Processor (VSP3)

    It was virtually impossible for image signal processors in the early 1980s to handle fast and sophisticated video codec processes because they had simple filtering capabilities. Anticipating that video codec processors would play an important role in the future multimedia era, Tadayoshi Enomoto began working on dedicated digital video codec processors in 1984. Tadayoshi Enomoto and Hachiro Yamada, constructed the world’s first video codec processor, a real-time, programmable video signal processor (P-VSP) with full video coding functions [1987]. Since then, they have been working on developing video codec processors and have contributed to many developments for high-speed circuit techniques, low-power techniques, architectures and signal processing for such processors.

    Among their many contributions, programmable video codec architecture is the most significant. This architecture, which was first used in a P-VSP, was well suited for a variety of both video standards and applications. Consequently, the successful development of the P-VSP LSI opened up new vistas for their application. This LSI has also motivated many companies to begin developing their own video codec processors. Therefore, the programmable video codec architecture has become the de facto standard for video codec processors. Namely, it has been used in many mass-produced video codec processors for teleconference systems, DVD recorders, cellular phones and high-definition TV video cameras.

    Parallel block-level pipeline architecture is another of their outstanding achievements [1995, 1993]. It is indispensable for small, high-speed, low-power video codec processors. This architecture comprises first and second pipelined processors and can simultaneously execute two separate coding processes, thereby shortening the processing time. Thus, many leading companies have adopted this architecture.

    In addition, a teleconference system using two S-VSP chips was constructed by his group and commercialized by NEC.



Publications

[1] T. Enomoto, M. Yamashina, T. Kunio, I. Tamitani, H. Harasaki, Y. Endo, T. Nishitani, M. Satoh, and K. Kikuchi、A microprogrammable realtime video signal processor (VSP) LSI for motion compensation and vector quantization、1987、Proc. of Custom Integrated Circuits Conference (CICC'87), pp.303-306, Portland, OR, USA, May 1987
[2] Masato Motomura and Tadayoshi Enomoto、Motion Picture Coder and System for Controlling、1995、US Patent No.5,394,189, Feb. 28, 1995
[3] T. Enomoto et al.、A 300 MHz, 16bit, Programmable Video Signal Processor ULSI for a Single Chip Teleconference Systems、1993、Proc. of the European Solid-State Circuits Conference (ESSCIRC'93), pp.94-97, Seville, Spain, Sept. 1993

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Electronics & Devices
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1996
Japanese embassy in Peru was attacked by guerilla.
1996
The Democratic Party of Japan was formed.
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